In present day microprocessor technology, a whole processor may be contained on a single chip. A microprocessor is usually connected with an associated main storage unit through a storage controller which may be an independent integrated circuit chip or it may be contained on the same chip as the processor. In any event, storage channel or bus between processor and main storage through the storage controller is a parallel data bus.
In the microprocessor technology, the main storage unit cannot be readily accessed for testing, debugging, and consequent data modification. Accordingly, present microprocessor systems have to a limited extent relied on software routines in the microprocessor system for testing purposes. Such software routines cannot be used for debugging because they require an operational system. They also have limitations in that they cannot check for certain types of hardware errors. Another testing and debugging approach has been to attach specialized apparatus to the parallel data bus of the system. However, as the technology moves toward 32-bit parallel buses, the specialized hardware would have to have a very wide interface and run at the system's speed. Such hardware would not be very economical.
The system of the present invention provides an approach which does not require costly specialized hardware, does not require a wide accessing bus nor extensive software routines stored in the system. It relies on a serial bus to access main storage as well as other I/O devices which completely bypasses the main parallel data bus of the system.
With respect to prior art, U.S. Pat. Nos. 4,322,812 entitled "Digital Data Processor Providing for Monitoring, Changing and Loading of RAM Instruction Data", Davis et al, filed Oct. 16, 1979, and 4,326,251 entitled "Monitoring System for a Digital Data Processor", Davis et al, filed Oct. 16, 1979, should be noted. Their only significance is that they appear to utilize serial data strings for testing purposes. However, these serial data strings are transmitted over serial data buses from main memory of the system to comparator apparatus which compares the accessed data to some form of reference data.